The present invention relates to a technique which is effective for application to a semiconductor integrated circuit device, hereafter referred to as an "IC", and more particularly, to a fabrication technique which is effective for application to an IC provided with an insulated gate field effect transistor, a metal insulator semiconductor field effect transistor hereinafter referred to as a "MISFET".
In the MISFET, there arises a problem in the geometric overlap between a gate electrode and source and drain regions. This problem becomes serious especially in case the source and drain regions of a fine MISFET having a channel length of 1.0 .mu.m are formed by an ion implantation using the gate electrode as a mask.
With an annealing treatment after the implantation, implanted impurities will diffuse below the gate electrode, i.e., into a channel region. As a result, an effective channel length is reduced to induce a short channel effect.
Because of the high diffusion velocity of boron ions in silicon, the short channel effect becomes an especially serious problem in a fine P-channel MISFET having boron ion implanted in forming the source and drain regions.